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hyb39s512400at(l) hyb39s512800at(l) hyb39s512160at(l) 512-mbit synchronous dram sdram data sheet, rev. 1.4, jan. 2006 memory products
edition 2006-01 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2006. all rights reserved. attention please! the information herein is given to describe certain co mponents and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology , delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain da ngerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safe ty or effectiveness of that device or system. life support devices or systems are intended to be implanted in the hu man body, or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
template: mp_a4_s_rev321 / 3 / 2005-10-05 hyb39s512400at(l) hyb39s512800at(l) hyb39s512160at(l) revision history: rev. 1.4 2006-01 previous version: rev 1.3 2004-03 page subjects (major cha nges since last revision) all data sheet only for -7.5 and -8 speed we listen to your comments any information within this do cument that you feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the qualit y of this document. please send us your proposal (including a reference to this document) to: techdoc.mp@infineon.com
hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram data sheet 4 rev. 1.4, 2006-01 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 signal pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 package p-tsopii-54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 operation definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3 mode register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3.1 burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.5 operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.5.1 read and write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.5.2 dqm function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.5.3 suspend mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.5.4 power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.2 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
data sheet 5 rev. 1.4, 2006-01 hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram table 1 performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3 pin configuration of the sdram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4 truth table: operation command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 5 mode register definition (ban[1:0] = 00 b ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 6 burst length and sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 7 bank selection by address bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 8 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 9 input and output capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 10 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 11 i dd conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 12 i dd specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 13 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
data sheet 6 rev. 1.4, 2006-01 hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram figure 1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 2 block diagram for 128m x 4 sdram (13/12/2 addressing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 3 block diagram for 64m x 8 sdram (13/11/2 addressing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 4 block diagram for 32m x 16 sdram (13/10/2 addressing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 5 measurement conditions for t ac and t oh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 6 bank activate command cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 7 burst read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 8 read interrupted by a read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 9 read to write interval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 10 minimum read to write interval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 11 non-minimum read to write interval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 12 burst write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 13 write interrupted by a write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 14 write interrupted by a read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 15 burst write with auto-precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 16 burst read with auto-precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 17 ac parameters for a write timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 18 ac parameters for a read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 19 mode register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 20 power on sequence and auto refresh (cbr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 21 clock suspension during burst read cas latency = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 22 clock suspension during burst read cas latency = 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 23 clock suspension during burst write cas latency = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 24 clock suspension during burst write cas latency = 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 25 power down mode and clock suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 26 self refresh (entry and exit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 27 auto refresh (cbr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 28 cas latency = 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 29 cas latency = 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 30 cas latency = 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 31 cas latency = 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 32 cas latency = 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 33 cas latency = 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 34 cas latency = 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 35 cas latency = 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 36 cas latency = 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 37 full page burst read, cas latency = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 38 full page burst write, cas latency = 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 39 package outline p-tsopii-54-1 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 list of figures
data sheet 7 rev. 1.4, 2006-01 10082003-l1gd-pvi5 hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram overview 1overview this chapter lists all main features of the produc t family hyb39s512[40/80/ 16]0at(l) and the ordering information. 1.1 features ? fully synchronous to positive clock edge ? 0 to 70 c operating temperature ? four banks controlled by ba0 & ba1 ? programmable cas latency: 2 & 3 ? programmable wrap sequence: sequential or interleave ? programmable burst length: 1, 2, 4, 8 and full page ? multiple burst read with single write operation ? automatic and controlled precharge command ? data mask for read / write control ( 4, 8) ? data mask for byte control ( 16) ? auto refresh (cbr) and self refresh ? power down and clock suspend mode ? 8192 refresh cycles / 64 ms (7.8 ms) ? random column address every clk ( 1-n rule) ? single 3.3 v 0.3 v power supply ? lvttl interface ? plastic packages:p-tsopii-54 400mil width (x4, x8, x16) 1.2 description the hyb 39s512[40/80/16]0at(l) are four ban k synchronous dram?s organized as 4 banks 32mbit 4, 4 banks 16mbit 8 and 4 banks 8mbit 16 respectively. these synchronous devices achieve high speed data transfer rates for cas-latencies by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a sys tem clock. the chip is fabricat ed with infineon?s advanced 0.14 m 512mbit dram process technology. the device is designed to comply with all industry stand ards set for synchronous dram products, both electrically and mechanically. all of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. operating the four memory banks in an interleave fashio n allows random access operation to occur at higher rate than is possible with standard drams. a sequential and gapless data rate is possible depending on burst length, cas latency and speed grade of the device. auto refresh (cbr) and self refresh operation are su pported. these devices op erates with a single 3.3 v 0.3 v power supply. all 512mbit components are housed in p-tsopii-54 packages. table 1 performance part number speed code ?7.5 ?8 unit speed grade pc133?333 pc100?222 ? max. clock frequency @cl3 f ck 133 125 mhz t ck3 7.5 8 ns t ac3 5.4 6 ns @cl2 t ck2 10 10 ns t ac2 66ns
hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram overview data sheet 8 rev. 1.4, 2006-01 10082003-l1gd-pvi5 table 2 ordering information type speed grade package description hyb 39s512400at-7.5 pc133-333-520 p-tsop-54-1 (400mil) 133mhz 4b 32m 4 sdram hyb 39s512400at-8 pc100-222-620 p-tsop-54-1 (400mil) 125mhz 4b 32m 4 sdram hyb 39s512800at-7.5 pc133-333-520 p-tsop-54-1 (400mil) 133mhz 4b 16m 8 sdram hyb 39s512800at-8 pc100-222-620 p-tsop-54-1 (400mil) 125mhz 4b 16m 8 sdram hyb 39s512160at-7.5 pc133-333-520 p-tsop-54-1 (400mil) 133mhz 4b 8m 16 sdram hyb 39s512160at-8 pc100-222-620 p-tsop-54-1 (400mil) 125mhz 4b 8m 16 sdram hyb 39s512xx0atl pc100-xxx-620 p-tsop-54-1 (4 00mil) low power vers ions (on request)
data sheet 9 rev. 1.4, 2006-01 10082003-l1gd-pvi5 hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram pin configuration 2 pin configuration this chapter contains the pin conf iguration table, the tsop package drawing and the block diagrams. 2.1 signal pin description listed below are the pin configurations sect ions for the various signals of the sdram table 3 pin configuration of the sdram pin type signal polarity function clk input pulse positive edge clock input the system clock input. all of the sdram inputs are sampled on the rising edge of the clock. cke input level active high clock enable activates the clk signal when high and deactivates the clk signal when low, thereby initiating either the power down mode, suspend mode, or the self refresh mode. cs input pulse active low chip select cs enables the command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. ras cas we input pulse active low command signals when sampled at the positive rising edge of the clock, cas , ras , and we define the command to be executed by the sdram. a0 - a12 input level ? address inputs during a bank activate command cycle, a0-a12 define the row address (ra0-ra12) when sampled at the rising clock edge. during a read or write command cycl e, a0-an define t he column address (ca0-can) when sampled at the risi ng clock edge. can depends upon the sdram organization: 64m x4sdram can = ca9, ca11 (page length = 2048 bits 32m x8sdram can = ca9 (page length = 1024 bits) 16m x16sdram can = ca8 (page length = 512 bits) in addition to the column address, a10 (= ap) is used to invoke the autoprecharge operation at the end of th e burst read or write cycle. if a10 is high, autoprecharge is selected and ba0, ba1 defines the bank to be precharged. if a10 is low, autoprecharge is disabled. during a precharge command cycle, a10 (= ap) is used in conjunction with ba0 and ba1 to control which bank(s ) to precharge. if a10 is high, all four banks will be precharg ed regardless of the st ate of ba0 and ba1. if a10 is low, then ba0 and ba1 are us ed to define which bank to precharge. ba0, ba1 input level ? bank select bank select inputs. bank address inpu ts selects which of the four banks a command applies to. dqx input output level ? data input/output data input/output pins operate in the same manner as on edo or fpm drams.
hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram pin configuration data sheet 10 rev. 1.4, 2006-01 10082003-l1gd-pvi5 dqm ldqm udqm input pulse active high data mask the data input/output mask places the dq buffers in a high impedance state when sampled high. in read mode, dqm has a latency of two clock cycles and controls the output buffers like an output enable. in write mode, dqm has a latency of zero and operates as a word mask by allowing input data to be written if it is low but bl ocks the write operat ion if dqm is high. one dqm input is present in x4 and x8 sdrams, ldqm and udqm controls the lower and u pper bytes in x16 sdrams. v dd v ss supply ? ? power and ground power and ground for the input buffers and the core logic (3.3 v) v ddq v ssq supply ? ? power and ground for dqs isolated power supply and ground fo r the output buffers to provide improved noise immunity. nc ? ? ? not connected no internal electrical connection is present. table 3 pin configuration of the sdram (cont?d) pin type signal polarity function
data sheet 11 rev. 1.4, 2006-01 10082003-l1gd-pvi5 hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram pin configuration 2.2 package p-tsopii-54 listed below are the pin outs of the tsop packages. figure 1 pin configuration 3 0 0 6 $ $ $ 1 ! ! 0 ! ! ! ! 6 $ $ 6 $ $ 1 $ 1 $ 1 6 3 3 1 $ 1 $ 1 6 $ $ 1 $ 1 $ 1 6 3 3 1 $ 1 6 $ $ , $ 1 - # ! 3 7 % 2 ! 3 # 3 " ! " ! " ! " ! # 3 2 ! 3 7 % # ! 3 . # 6 $ $ . # 6 3 3 1 $ 1 . # 6 $ $ 1 $ 1 . # 6 3 3 1 $ 1 . # 6 $ $ 1 6 $ $ ! ! ! ! ! ! 0 $ 1 6 $ $ 6 $ $ " ! " ! # 3 2 ! 3 7 % # ! 3 . # 6 $ $ . # 6 3 3 1 $ 1 . # 6 $ $ 1 . # . # 6 3 3 1 $ 1 . # 6 $ $ 1 6 $ $ ! ! ! ! ! ! 0 . # 6 3 3 . # ! ! ! ! ! 6 3 3 6 3 3 1 . # $ 1 6 $ $ 1 . # . # 6 3 3 1 . # $ 1 6 $ $ 1 . # 6 3 3 . # # , + $ 1 - # + % ! ! ! ! ! ! # + % $ 1 - # , + . # 6 3 3 . # 6 $$ 1 $ 1 . # 6 3 3 1 $ 1 . # 6 $$ 1 $ 1 . # 6 3 3 1 6 3 3 ! ! ! ! ! $ 1 6 3 3 6 3 3 ! ! ! # + % 5 $ 1 - # , + . # 6 3 3 $ 1 6 $ $1 $ 1 $ 1 6 3 3 1 $ 1 $ 1 6 $ $1 $ 1 $ 1 6 3 3 1 6 3 3 ! ! ! ! ! $ 1 4 3 / 0 ) ) m i l x m i l m m p i t c h - x - x - x
hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram pin configuration data sheet 12 rev. 1.4, 2006-01 10082003-l1gd-pvi5 2.3 block diagrams the block diagrams for 8 16 are shown below. ? block diagram for 128m x 4 sdram (13/12/2 addressing) ? block diagram for 64m x 8 sdram (13/11/2 addressing) figure 2 block diagram for 128m x 4 sdram (13/12/2 addressing) 03%6 0hpru\ $uud\ %dqn [%lw 0hpru\ $uud\ %dqn [%lw 0hpru\ $uud\ %dqn [%lw &roxpq $gguhvv &rxqwhu 5rz 'hfrghu 0hpru\ $uud\ %dqn [%lw &roxpq 'hfrghu 6hqvh dpsolilhu ,2%xv 5rz 'hfrghu 6hq vh dpsolilhu ,2 %xv 5rz 'hfrghu 5rz 'hfrghu &roxpq 'hfrghu 6hqvh dpsolilhu ,2 %xv 5rz $gguhvv %xiihu &roxpq $gguhvv %xiihu 5hiuhvk &rxqwhu 6hqvh dpsolilhu ,2 %xv $ $ %$ %$ $ $ $ 3$$ %$ %$ &roxpq $gguhvvhv 5rz $gguhvvhv ,qsxw %xiihu 2xwsxw %xiihu '4 '4 &rqwuro /rjlf 7lplqj *hqhudwru &/. &.( &6 5$6 &$6 :( '40 &roxpq 'hfrgh u &rox pq 'hfrghu [ [ [ [
data sheet 13 rev. 1.4, 2006-01 10082003-l1gd-pvi5 hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram pin configuration figure 3 block diagram for 64m x 8 sdram (13/11/2 addressing) 03%6 0hpru\ $uud\ %dqn [%lw 0hpru\ $uud\ %dqn [%lw 0hpru\ $uud\ %dqn [%lw &roxpq $gguhvv &rxqwhu 5rz 'hfrghu 0hpru\ $uud\ %dqn [%lw &roxpq 'hfrghu 6hqvh dpsolilhu ,2%xv 5rz 'hfrghu 6hq vh dpsolilhu ,2 %xv 5rz 'hfrghu 5rz 'hfrghu &roxpq 'hfrghu 6hqvh dpsolilhu ,2 %xv 5rz $gguhvv %xiihu &roxpq $gguhvv %xiihu 5hiuhvk &rxqwhu 6hqvh dpsolilhu ,2 %xv $ $ %$ %$ $ $ $ 3$ %$ %$ &roxpq $gguhvvhv 5rz $gguhvvhv ,qsxw %xiihu 2xwsxw %xiihu '4 '4 &rqwuro /rjlf 7lplqj *hqhudwru &/. &.( &6 5$6 &$6 :( '40 &roxpq 'hfrgh u &rox pq 'hfrghu [ [ [ [
hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram pin configuration data sheet 14 rev. 1.4, 2006-01 10082003-l1gd-pvi5 figure 4 block diagram for 32m x 16 sdram (13/10/2 addressing) 03%6 0hpru\ $uud\ %dqn [%lw 0hpru\ $uud\ %dqn [%lw 0hpru\ $uud\ %dqn [%lw &roxpq $gguhvv &rxqwhu 5rz 'hfrghu 0hpru\ $uud\ %dqn [%lw &roxpq 'hfrghu 6hqvh dpsolilhu ,2 %xv 5rz 'hfrghu 6hqvh dpsolilhu ,2 %xv 5rz 'hfrghu 5rz 'hfrghu &roxpq 'hfrghu 6hqvh dpsolilh u ,2%xv 5rz $gguhvv %xiihu &roxpq $gguhvv %xiihu 5hiuhvk &rxqwhu 6hqvh dpsolilhu ,2 %xv $ $ %$ %$ $ $ $3 %$ %$ &roxpq $gguhvvhv 5rz $gguhvvhv ,qsxw %xiihu 2xwsxw %xiihu '4 '4 &rqwuro /rjlf 7lplqj *hqhudwru &/. &.( &6 5$6 &$6 :( '408 '40/ &roxpq 'hfrghu &roxpq 'hfrghu [ [ [ [
data sheet 15 rev. 1.4, 2006-01 10082003-l1gd-pvi5 hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram functional description 3 functional description this chapter list all defined commands and their usage for this synchronous dram family. 3.1 operation definition all sdram operations are defined by states of control signals cs , ras , cas , we , and dqm at the positive edge of the clock. the following list shows the truth table for the operation commands. table 4 truth table: operation command operation devics state cke n-1 1)2) 1) v = valid, x = don?t care, l = low level, h = high level 2) cken signal is input level when commands are provided, cken-1 signal is input level one clock before the commands are provided. cke n1)2 ) dqm 1)2) ba0 ba11) 2) ap= a101)2 ) addr 1)2) cs 1)2) ras 1)2) cas 1)2) we 1)2) bank active idle 3) 3) this is the state of the ban ks designated by ba0, ba1 signals. hxxv v vllhh bank precharge any h x x v l x l l h l precharge all any h x x x h x l l h l write active 3) h x x v l v l h l l write with autopre- charge active 3) h x x v h v l h l l read active 3) h x x v l v l h l h read with autopre- charge active 3) h x x v h v l h l h mode register set idle h x x v v v l l l l no operation any h x x x x x l h h h burst stop active h x x x x x l h h l device deselect any h x x x x x h x x x auto refresh idle h h x x x x l l l h self refresh entry idle h l x x x x l l l h self refresh exit idle (self refr.) lhxx x xhxxx lh h x clock suspend entry active l h x x x x x x x x power down entry (precharge or active standby) idle hlxx x x hx x x active 4) lh h h clock suspend exit active l h x x x x x x x x power down exit any (power down) lhxx x xhxxx lh h l data write/output enable active h x l x x x x x x x data write/output disable active h x h x x x x x x x
hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram functional description data sheet 16 rev. 1.4, 2006-01 10082003-l1gd-pvi5 3.2 initialization the default power on state of the mode register is su pplier specific and may be u ndefined. the following power on and initialization sequence guarante es the device is preconditioned to each users specific needs. like a conventional dram, the synchronous dram must be powered up and initialized in a predefined manner. during power on, all vdd and v ddq pins must be built up simultaneously to the specified voltage when the input signals are held in the ?nop? state. the power on voltage must not exceed v dd + 0.3 v on any of the input pins or v dd supplies. the clk signal must be started at the same time. after power on, an initial pause of 200 s is required followed by a precharge of all banks using the precha rge command. to prevent data contention on the dq bus during power on, it is required that the dqm and cke pins be held high during the initial pause period. once all banks have been precharged, the mode register set comm and must be issued to in itialize the mode register. a minimum of eight auto refresh cycles (cbr) are also re quired.these may be done before or after programming the mode register. failure to follow these steps may lead to unpredictable start-up modes. 4) power down mode can not be entered in a burst cycle. when th is command asserted in the burst mode cycle device is in clock suspend mode.
data sheet 17 rev. 1.4, 2006-01 10082003-l1gd-pvi5 hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram functional description 3.3 mode register definition the mode register designates the operation mode at the read or write cycle. this register is divided into four fields. first, a burst length field which sets the length of the burst, second, an addressing selection bit which programs the column access sequence in a burst cycle (interleaved or sequential). third, a cas latency field to set the access time at clock cycle. fourth, an operation mode fi eld to differentiate between normal operation (burst read and burst write) and special burst read and single writ e mode. after the initial power up, the mode set operation must be done before any activate command. any content of the mode register can be altered by re-executing the mode set command. all banks must be in precharged stat e and cke must be high at least one clock before the mode set operation. after the mode register is set, a standby or nop command is required. low signals of ras, cas, and we at the positive edge of t he clock activate the mode set operation. address input data at this timing defines parameters to be set as shown in the previous table. table 5 mode register definition (ban[1:0] = 00 b ) field bits type description bl [2:0] w burst length number of sequential bits per dq re lated to one read/write command, see note: all other bit combinations are reserved 000 b 1 , 001 b 2 , 010 b 4 , 011 b 8 , 111 b full page (sequential burst type only) , bt 3w burst type see table 6 for internal address sequence of low order address bits. 0 b sequential , 1 b interleaved , cl [6:4] w cas latency number of full clocks from read co mmand to first data valid window. note: all other bit combinations are reserved. 010 b 2 , 011 b 3 , mode [12:7] w operation mode note: all other bit combinations are reserved. 0 b burst read/burst write , 1 b burst read/single write , -0"3 "! "! ! ! ! ! ! ! ! ! ! ! ! ! ! ! regaddr w w w w "4 ", #, -/$%
hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram functional description data sheet 18 rev. 1.4, 2006-01 10082003-l1gd-pvi5 3.3.1 burst length note: 1. for a burst length of two, a1-ai selects the two-data-ele ment block; a0 selects the first access within the block. 2. for a burst length of four, a2-ai selects the four-data- element block; a0-a1 selects the first access within the block. 3. for a burst length of eight, a3-ai selects the eight-data - element block; a0-a2 select s the first access with in the block. 4. whenever a boundary of the block is reached withi n a given sequence above, the following access wraps within the block. table 6 burst length and sequence burst length starting column address order of accesses within a burst a2 a1 a0 type=sequential type=interleaved 200?10?1 11?0 1?0 4 0 0 0?1?2?3 0?1?2?3 0 1 1?2?3?0 1?0?3?2 1 0 2?3?0?1 2?3?0?1 1 1 3?0?1?2 3?2?1?0 8 0 0 0 0?1?2?3?4?5?6?7 0?1?2?3?4?5?6?7 0 0 1 1?2?3?4?5?6?7?0 1?0?3?2?5?4?7?6 0 1 0 2?3?4?5?6?7?0?1 2?3?0?1?6?7?4?5 0 1 1 3?4?5?6?7?0?1?2 3?2?1?0?7?6?5?4 1 0 0 4?5?6?7?0?1?2?3 4?5?6?7?0?1?2?3 1 0 1 5?6?7?0?1?2?3?4 5?4?7?6?1?0?3?2 1 1 0 6?7?0?1?2?3?4?5 6?7?4?5?2?3?0?1 1 1 1 7?0?1?2?3?4?5?6 7?6?5?4?3?2?1?0 fullpage n cn, cn+1, cn+2 .... not supported
data sheet 19 rev. 1.4, 2006-01 10082003-l1gd-pvi5 hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram functional description 3.4 commands refresh mode sdram has two refresh modes, auto refresh and self refr esh. auto refresh is similar to the cas -before-ras refresh of conventional drams. all banks must be prec harged before applying any refresh mode. an on-chip address counter increments the word and the bank addr esses and no bank information is required for either refresh mode. the chip enters the auto refresh mode, when ras and cas are held low and cke and we are held high at a positive clock transition. the mode restores word line after the refresh and no external precharge command is necessary. a minimum t rc time is required between two automatic refreshes in a burst refresh mode. the same rule applies to any access command after the automatic refresh operation. the chip has an on-chip timer and the self refresh mode is available. the mode restor es the word lines after ras , cas , and cke are low and we is high at a positive clock transition. all external control signals including the clock are disabled. returning cke to high enables the clock and initiates the refresh exit operation. after the exit command, at least one t rc delay is required prior to any access command. auto precharge two methods are available to precharge sdrams. in an automatic precharge mode, the cas timing accepts one extra address, ca10, to determine whether the chip restor es or not after the operation. if ca10 is high when a read command is issued, the read with auto-precharge f unction is initiated. if ca10 is high when a write command is issued, the write with auto-precharge func tion is initiated. the sdra m automatically enters the precharge operation a time delay equal to t wr (?write recovery time?) after the last data in. a burst operation with auto-precharge may only be interr upted by a burst start to another bank. it must not be interrupted by a precharge or a burst stop command. precharge command there is also a separate precharge command available. when ras and we are low and cas is high at a clock timing, it triggers the precharge operation. three a ddress bits, ba0, ba1 and a10 are used to define banks as shown in the following list. the precharge command can be imposed one clock before the last data out for cas latency = 2 and two clocks before the last data out for cas latency = 3. writes requir e a time delay twr (?write recovery time?) of 2 clocks minimum from the last data out to apply the precharge command. burst termination once a burst read or write operation has been initiated, there are several methods in which to terminate the burst operation prematurely. these methods include using ano ther read or write command to interrupt an existing burst operation, use a precharge command to interrupt a bur st cycle and close the active bank, or using the burst stop command to terminate the existing burst operation but leave the bank open for future read or write commands to the same page of the active bank. when interrupting a burst with another read or write command care must be taken to avoid dq contention. the bu rst stop command, however, has the fewest restrictions table 7 bank selection by address bits a10 ba0 ba1 0 0 0 bank 0 0 0 1 bank 1 0 1 0 bank 2 0 1 1 bank 3 1 xxall banks
hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram functional description data sheet 20 rev. 1.4, 2006-01 10082003-l1gd-pvi5 making it the easiest method to use when terminating a burst operation before it has been completed. if a burst stop command is issued during a burst write operation, then any residual data from the burst write cycle will be ignored. data that is presen ted on the dq pins before th e burst stop command is regist ered will be written to the memory. 3.5 operations 3.5.1 read and write when ras is low and both cas and we are high at the positive edge of the clock, a ras cycle starts. according to address data, a word line of the sele cted bank is activated and all of sens e amplifiers associated to the wordline are set. a cas cycle is tr iggered by setting ras high and cas low at a clock timing after a necessary delay, t rcd , from the ras timing. we is used to define either a read (we = h) or a write (we = l) at this stage. sdram provides a wide variety of fast access modes. in a single cas cycle, serial data read or write operations are allowed at up to a 166 mhz data rate. the numbers of serial data bits are the burst length programmed at the mode set operation, i.e., one of 1, 2, 4 and 8 and full page. column addresses are segmented by the burst length and serial data accesses are done within this boundary. the first column address to be accessed is supplied at the cas timing and the subsequent addresses are genera ted automatically by the programmed burst length and its sequence. for example, in a burst le ngth of 8 with interleave sequence, if the first address is ?2?, then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5. full page burst operation is only possible using the sequent ial burst type and page length is a function of the i/o organization and column addressing. full page burst operat ion does not self terminate once the burst length has been reached. in other words, unlike burst lengths of 2, 4 and 8, full page burst continues until it is terminated using another command. similar to the page mode of conventional drams, burs t read or write accesses on any column address are possible once the ras cycle latche s the sense amplifiers. the maximum t ras or the refresh interval time limits the number of random column accesses. a new burst access can be done even before the previous burst ends. the interrupt operation at every clock cycle is supported. wh en the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. an interrupt which accompanies an operation change from a read to a write is po ssible by exploiting dqm to avoid bus contention. when two or more banks are activated sequentially, inte rleaved bank read or write o perations are possible. with the programmed burst length, alternate access and precha rge operations on two or more banks can realize fast serial data access modes among many different pages. once two or more banks are activated, column to column interleave operation can be performed between different pages. 3.5.2 dqm function dqm has two functions for data i/o read and write operatio ns. during reads, when it turns to ?high? at a clock timing, data outputs are disabled and become high imp edance after two clock delay (dqm data disable latency t dqz ). it also provides a data mask functi on for writes. when dqm is activated, the write operation at the next clock is prohibited (dqm write mask latency t dqw = zero clocks). 3.5.3 suspend mode during normal access mode, cke is held high enabling the clock. when cke is low, it freezes the internal clock and extends data read and write operations. one clock de lay is required for mode entry and exit (clock suspend latency t csl ).
data sheet 21 rev. 1.4, 2006-01 10082003-l1gd-pvi5 hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram functional description 3.5.4 power down in order to reduce standby power consumption, a power down mode is available. all banks must be precharged and the necessary precharge delay ( t rp ) must occur before the sdram ca n enter the power down mode. once the power down mode is initiated by ho lding cke low, all of the receiver circuits except clk and cke are gated off. the power down mode does not perform any refresh operations, therefore the device can?t remain in power down mode longer than the refresh period ( t ref ) of the device. exit from this mode is performed by taking cke ?high?. one clock delay is required for power down mode entry and exit.
hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram electrical characteristics data sheet 22 rev. 1.4, 2006-01 10082003-l1gd-pvi5 4 electrical characteristics 4.1 operating conditions attention: stresses above the max. values listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum ratings are absolute ratings; exceeding only one of these values maycause irreversible damage to the integrated circuit. table 8 absolute maximum ratings parameter symbol values unit note/ test condition min. max. voltage on i/o pins relative to v ss v in , v out ?1.0 +4.6 v power supply voltage v dd , v ddq ?1.0 +4.6 v operating temperature t a 0+70 c storage temperature range t stg ?55 +150 c power dissipation per sdram component p d ?1 w data out current (short circuit) i out ?50ma table 9 input and output capacitances 1) 1) t a = 0 to 70 c; v dd, v ddq = 3.3 v 0.3 v, f = 1 mhz parameter symbol values 2) 2) capacitance values are shown for tsop-54 packages. capac itance values for tfbga packages are lower by 0.5 pf unit min. max. input capacitance: ck, ck c i1 2.5 3.5 pf input capacitance (a0-a12, ba0,ba1,ras , cas , we , cs , cke, dqm) c i2 2.5 3.8 pf input / output capacitance (dq) c i0 4.0 6.0 pf
data sheet 23 rev. 1.4, 2006-01 10082003-l1gd-pvi5 hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram electrical characteristics table 10 dc characteristics 1) 1) t a = 0 to 70 c parameter symbol values unit note/ test condition min. max. supply voltage v dd 3.0 3.6 v 2) 2) all voltages are referenced to v ss i/o supply voltage v ddq 3.0 3.6 v 2) input high voltage v ih 2.0 v ddq + 0.3 v 2)3) 3) v ih may overshoot to v ddq + 2.0 v for pulse width of < 4ns with 3.3 v. v il may undershoot to -2.0 v for pulse width < 4.0 ns with 3.3 v. pulse width measured at 50% points with amplitude measured peak to dc reference. input low voltage v il ?0.3 0.8 v 2)3) output high voltage ( i out = ?4.0 ma) v oh 2.4 ? v 2) output low voltage ( i out = 4.0 ma) v ol ?0.4 v 2) input leakage current, any input (0 v < v in < v dd , all other inputs = 0 v) i il ?5 5 a output leakage current (dqs are disabled, 0 v < v out < vddq) i ol ? 55 a table 11 i dd conditions parameter symbol operating current single bank, burst length 4 i o =0 ma i dd1 precharge standby current in power down mode cs = v ih,min ; cke v il,max i dd2p precharge standby current in non-power down mode cs = v ih(min.) , cke v ih(min.) i dd2n active power-down standby current one bank active state(max. 4 banks) cs = v ih(min.) ,cke v ih(min.) i dd3n active standby current one bank active state (max. 4 banks) cs = v ih(min.) , cke v il(max.) i dd3p burst operating current read command cycling i dd4 auto refresh current auto refresh command cycling t rfc = t rfc(min.) i dd5 self refresh current self refresh mode, cke = 0.2 v, t ck = infinity 16 i dd6
hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram electrical characteristics data sheet 24 rev. 1.4, 2006-01 10082003-l1gd-pvi5 table 12 i dd specifications symbol ?7.5 ?8 unit note/test condition 1) 1) t a = 0 to 70 c; v ss = 0 v, v dd , v ddq = +3.3 v 0.3 v typ. max. typ. max. i dd1 123 145 95 110 ma 2)3) 2) these parameters depend on the cycle rate. all values are measured at 133 mhz for ?-7? and ?-7.5? and at 100 mhz for ?- 8? components with the outputs open. input signals are changed once during t ck . 3) these parameters are measured with cont inuous data stream during read access an d all dq toggling. cl=3 and bl=4 is assumed and the v ddq current is excluded. i dd2p 0.6 3 0.6 3 ma 2) i dd2n 23 31 19 25 ma 2) i dd3n 26 35 21 30 ma 2) i dd3p 2424ma 2) i dd4 97 123 79 100 ma 2)3) i dd5 255 300 240 270 ma t rfc = t rfc(min.) 4) 4) t rfc = t rfc(min.) ?burst refresh? i dd6 2.1 4 2.1 4 ma standard
data sheet 25 rev. 1.4, 2006-01 10082003-l1gd-pvi5 hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram electrical characteristics 4.2 ac characteristics table 13 ac characteristics 1)2)3) parameter symbol ?7.5 ?8 unit notes pc133 ? 333 pc100 ? 222 min. max. min. max. clock and clock enable clock cycle time t ck 7.5 10 ? ? 8 10 ? ? ns ns cl3 cl2 clock frequency f ck ? ? 133 100 ? ? 125 100 mhz mhz cl3 cl2 access time from clock t ac ? ? 5.4 6 ? ? 6 6 ns ns cl3 cl2 3)4)5) clock high pulse width t ch 2.5 ? 3 ? ns clock low pulse width t cl 2.5 ? 3 ? ns transition time t t 0.3 1.2 0.5 10 ns setup and hold times input setup time t is 1.5 ? 2 ? ns 6) input hold time t ih 0.8 ? 1 ? ns 6) cke setup time t cks 1.5 ? 2 ? ns 6) cke hold time t ckh 0.8 ? 1 ? ns 6) mode register set-up to active delay t rsc 2?2? t ck power down mode entry time t sb 07.508ns common parameters row to column delay time t rcd 20 ? 20 ? ns 7) row precharge time t rp 20 ? 20 ? ns 7) row active time t ras 45 100k 48 100k ns 7) row cycle time t rc 67 ? 70 ? ns 7) row cycle time duri ng auto refresh t rfc 67 70 ns activate(a) to activate(b) command period t rrd 15 ? 16 ? ns 7) cas (a) to cas (b) command period t ccd 1?1? t ck refresh cycle refresh period (8192 cycles) t ref ?64?64ms self refresh exit time t srex 1?1 t ck read cycle data out hold time t oh 3?3?ns 3)6) data out to low impedance time t lz 1?0?ns data out to high impedance time t hz 3738ns dqm data out disable latency t dqz ?2?2 t ck write cycle last data input to precharge (write without autoprecharge) t wr 15 ? 16 ? ns 8)
hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram electrical characteristics data sheet 26 rev. 1.4, 2006-01 10082003-l1gd-pvi5 figure 5 measurement conditions for t ac and t oh last data input to activate (write with auto precharge) t dal(min.) t ck 9) dqm write mask latency t dqw 0?0? t ck 1) t a = 0 to 70 c; v ss = 0 v, v dd , v ddq = 3.3 v 0.3 v, t t = 1 ns 2) for proper power-up see the opera tion section of this data sheet. 3) ac timing tests for lv-ttl versions have v il = 0.4 v and v ih = 2.4 v with the timing refere nced to the 1.4 v crossover point. the transition time is measured between v ih and v il . all ac measurements assume t t = 1 ns with the ac output load circuit shown in figure below. specified tac and toh pa rameters are measured with a 50 pf only, without any resistive termination and with an input signal of 1v / ns edge rate between 0.8 v and 2.0 v. 4) if clock rising time is longer than 1 ns, a time ( t t /2 - 0.5) ns has to be added to this parameter. 5) if t t is longer than 1 ns, a time ( t t - 1) ns has to be added to this parameter. 6) access time from clock tac is 4.6 ns for pc133 components with no termination and 0 pf load, data out hold time toh is 1.8 ns for pc133 components with no termination and 0 pf load. 7) this parameter determines the minimum r equired number of clock cycl es as follows: the requir ed number of clock cycles is given by the value of the specified parameter divided by t he period of the clock. non-integer values must be rounded up to the next greater integer value. 8) it is recommended to use two clock cycl es between the last data-in and the pr echarge command in case of a write command without au to-precharge. one clock cycle be tween the last data- in and the pr echarge command is also supported, but restricted to cycle time s tck greater or equal the specified t wr value, where t ck is equal to the actual system clock time. 9) when a write command with autoprec harge has been issued, a time of t dal(min.) has be fullfilled before the next activate command can be applied. for each of the terms, if not already an integer, round up to the next highest integer. t ck is equal to the actual system clock time. table 13 ac characteristics 1)2)3) parameter symbol ?7.5 ?8 unit notes pc133 ? 333 pc100 ? 222 min. max. min. max. clock 2.4 v 0.4 v in p u t is t t t output 1.4 v t lz ac t t ac oh t hz t 1.4 v cl t ch t ih t 1.4 v io.vsd
data sheet 27 rev. 1.4, 2006-01 10082003-l1gd-pvi5 hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram timing diagrams 5 timing diagrams figure 6 bank activate command cycle figure 7 burst read operation 2# (or, t 4 #!3latency "ank" 2ow!ddr !ctivate "ank" !ddress #ommand #,+ 4 ./0 ./0 2#$ t 4 #ol!ddr "ank" with!uto 0recharge 7rite" 4 304 "ank" 2ow!ddr !ctivate "ank" 2ow!ddr "ank! !ctivate "ank! 4 ./0 22$ t 4 4 304 #,+ 2ead! ./0 4 4 4 4 4 4 4 4 4 #ommand ./0 ./0 ./0 ./0 ./0 ./0 ./0 $/54! #+ latency t $1gs $/54! $/54! $/54! $/54! #+ latency t $1gs $/54! $/54! $/54! #!3 #!3
hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram timing diagrams data sheet 28 rev. 1.4, 2006-01 10082003-l1gd-pvi5 figure 8 read interrupted by a read figure 9 read to write interval 304 #,+ 2ead! 4 4 4 4 4 4 4 4 4 #ommand $/54! $/54" $/54" $/54" ./0 ./0 ./0 ./0 ./0 ./0 ./0 latency $1gs #+ t #+ latency t $1gs "urst,ength#!3latency #!3 #!3 2ead" $/54" $/54" $/54! $/54" $/54" $/54" #ommandscycles -inimumdelaybetweenthe2eadand7rite $/54! $1gs "urst,ength#!3latency $1-x #ommand #,+ ./0 2ead! 4 4 ./0 ./0 4 4 the7rite#ommand -ustbe(i :before $)." $)." 304 $)." $17 ./0 $1: t ./0 t 4 4 7rite" ./0 4 4 ./0 4 (or, 7ritelatency of$1-x
data sheet 29 rev. 1.4, 2006-01 10082003-l1gd-pvi5 hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram timing diagrams figure 10 minimum read to write interval figure 11 non-minimum read to write interval the7rite#ommand -ustbe(i :before !ctivate #!3 #+ latency t $1gs "urst,ength#!3latency #,+ $1- #ommand ./0 4 4 "ank! ./0 $1: t 4 4 $).! $).! $).! 304 $).! #lk)nterval 2ead! 7rite! 4 4 ./0 ./0 4 4 ./0 4 (or, t $17 ./0 #!3 latency #+ #!3 #+ latency t t $1gs $1gs $/54! "urst,ength#!3latency #,+ $1- #ommand ./0 2ead! 4 4 ./0 ./0 4 4 the7rite#ommand -ustbe(i :before $/54! $/54! $)." $)." $)." $)." 304 $)." $)." 2ead! $1: t ./0 4 4 7rite" ./0 4 4 ./0 4 (or, t $17
hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram timing diagrams data sheet 30 rev. 1.4, 2006-01 10082003-l1gd-pvi5 figure 12 burst write operation figure 13 write interrupted by a write %xtradataisignoredafter terminationofa"urst $).! 4 areregisteredonthesameclockedge 4hefirstdataelementandthe7rite ./0 "urst,ength#!3latency 4 #ommand $1gs #,+ $).! 4 ./0 $).! 7rite! 4 $).! ./0 4 304 4 ./0 ./0 4 ./0 ./0 4 ./0 4 dongtcare 1 clk interval 304 #,+ 4 4 4 4 4 4 4 4 4 #ommand ./0 ./0 ./0 ./0 ./0 ./0 $1gs "urst,ength#!3latency ./0 7rite! $).! $)." $)." $)." $)." 7rite" #lk)nterval
data sheet 31 rev. 1.4, 2006-01 10082003-l1gd-pvi5 hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram timing diagrams figure 14 write interrupted by a read figure 15 burst write with auto-precharge 4 ./0 $/54" $/54" )nputdataforthe7riteisignored $1gs latency #+ #!3 t dongtcare $).! dongtcare "urst,ength#!3latency #,+ $1gs #ommand latency #+ #!3 t ./0 4 $).! 7rite! dongtcare 2ead" 4 4 $/54" ./0 ./0 4 4 304 appearsontheoutputstoavoiddatacontention $/54" )nputdatamustberemovedfromthe$1gs atleastoneclockcyclebeforethe2eaddata $/54" $/54" ./0 $/54" ./0 $/54" 4 4 ./0 4 304 #,+ !ctive ./0 4 4 4 4 4 4 4 4 4 #ommand ./0 ./0 ./0 ./0 ./0 ./0 latency $1gs latency $1gs "urst,ength#!3latency #!3 #!3 "ank! 20 t 20 t "egin!uto0recharge "ankcanbereactivatedafter 7rite! !uto0recharge 72 t $).! $).! 72 t $).! $).! 20 t
hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram timing diagrams data sheet 32 rev. 1.4, 2006-01 10082003-l1gd-pvi5 figure 16 burst read with auto-precharge 304 #,+ with!0 ./0 4 4 4 4 4 4 4 4 4 #ommand $/54! $/54! $/54! $/54! ./0 ./0 ./0 ./0 ./0 ./0 ./0 latency $1gs #+ t $/54! #+ latency t $1gs $/54! $/54! $/54! "urst,ength#!3latency #!3 #!3 2ead! 20 t 20 t "ankcanbereactivatedafter "egin!uto0recharge 20 t
data sheet 33 rev. 1.4, 2006-01 10082003-l1gd-pvi5 hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram timing diagrams figure 17 ac parameters for a write timing !uto0recharge "ank" #ommand 7ritewith !ctivate 7ritewith !ctivate "ank! #ommand !uto0recharge "ank! #ommand #ommand "ank" !ddr !0 $1- $1 "3 (i : 2#$ t !x !x !x !x 2# t 2!x 2!x t !3 t !( 2"x 2"x #!x !ctivate 0recharge !ctivate 7rite #ommand #ommand "ank! "ank! #ommand "ank! "ank! #ommand 304 "x "x "x "x $3 t t $( !y !y !y !y t 72 2!y 2!y #"x 2!y 20 t 2!z 2!z 4 0recharge "egin!uto "ank! #,+ 7% #!3 2!3 #3 #+% #+ t #3 t #( #+3 t #( t t #, t 4 4 4 4 4 4 4 4 "ank" 0recharge "egin!uto t #+( 4 "urst,ength#!3,atency 4 4 4 4 4 4 4 4 4 4 4 4 4 2"y 2"y 22$ t !ctivate "ank" #ommand
hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram timing diagrams data sheet 34 rev. 1.4, 2006-01 10082003-l1gd-pvi5 figure 18 ac parameters for a read timing !# (i : $1 !ctivate #ommand "ank! 2eadwith "ank! #ommand !uto0recharge $1- !ddr !0 t 2#$ t ,: t t !3 2!x 2!x t !( #!x 22$ t #ommand "ank" 2eadwith !uto0recharge !ctivate "ank" #ommand !x !x "x !ctivate 304 #ommand "ank! "x t !# /( t (: t t 2!3 2# t 2"x 2"x 2"x (: t 2!y 2!y 4 t t "3 7% #!3 2!3 t #3 #+% #+3 t #( t t #3 #( #, #+ #,+ 4 4 4 4 4 0recharge "ank! "egin!uto 0recharge "ank" "egin!uto t #+( "urst,ength#!3,atency 4 4 4 4 4 4 4 4 20 t 0recharge "ank! #ommand
data sheet 35 rev. 1.4, 2006-01 10082003-l1gd-pvi5 hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram timing diagrams figure 19 mode register set 3et#ommand -ode2egister !ll"anks 0recharge #ommand !ny #ommand !ddress+ey 4 4 4 4 23# t 4 4 4 4 4 4 4 4 4 4 304 4 4 4 4 4 4 #!3,atency 4 4 4 "3"3 ! ! !! #3 7% #!3 2!3 #+% #,+
hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram timing diagrams data sheet 36 rev. 1.4, 2006-01 10082003-l1gd-pvi5 figure 20 power on sequence and auto refresh (cbr) )nputsmustbe stablefor s $1- !0 $1 !ddr "3 20 #ommand !ll"anks 0recharge (i : ^ ^ t st!uto2efresh #ommand ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 304 -ode2egister 3et#ommand !ddress+ey th!uto2efresh #ommand ^ ^ t 2# ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ #ommand !ny -inimumof2efresh#yclesarerequired 4 7% #!3 2!3 #3 #+% #,+ required ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 4 is ^ ^ ^ ^ ,evel (igh 4 4 4 4 4 4 4 4 #lockmin ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 4 ^ ^ ^ ^ 4 4 4 4 4 4 4 4 4 4 4 4
data sheet 37 rev. 1.4, 2006-01 10082003-l1gd-pvi5 hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram timing diagrams figure 21 clock suspension during burst read cas latency = 2 #ommand "ank! $1- !ddr $1 !0 "3 2ead #ommand "ank! !ctivate (i : 3uspend #ycle #lock !x #3, t !x #!x 2!x 2!x 304 t 3uspend #ycles 3uspend #ycles #lock !x #3, t #lock !x (: 4 7% #!3 2!3 #3 #+% #,+ #+ t 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 "urst,ength#!3,atency 4 4 4 4 4 4 #3, t
hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram timing diagrams data sheet 38 rev. 1.4, 2006-01 10082003-l1gd-pvi5 figure 22 clock suspension during burst read cas latency = 3 #3, $1- !ddr $1 !0 "3 "ank! !ctivate #ommand (i : #ommand "ank! 2ead !x t 2!x 2!x #!x (: t t 3uspend #ycle #lock 3uspend #ycles #lock #3, !x !x #lock 3uspend #ycles t #3, !x 304 4 7% #!3 2!3 #3 #+% #,+ #+ t 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 "urst,ength#!3,atency 4 4 4 4 4 4
data sheet 39 rev. 1.4, 2006-01 10082003-l1gd-pvi5 hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram timing diagrams figure 23 clock suspension during burst write cas latency = 2 "ank! $1- !ddr $1 !0 "3 $!x #ommand 7rite !ctivate #ommand "ank! (i : #lock #lock #ycle 3uspend 3uspend #ycles $!x #!x 2!x 2!x $!x #lock 3uspend #ycles $!x 304 4 7% #!3 2!3 #3 #+% #,+ #+ t 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 "urst,ength#!3,atency 4 4 4 4 4 4
hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram timing diagrams data sheet 40 rev. 1.4, 2006-01 10082003-l1gd-pvi5 figure 24 clock suspension during burst write cas latency = 3 #lock 3uspend #ycles "ank! $1-x !ddr $1 !!0 "! !ctivate #ommand "ank! (i : #lock #ycle 3uspend #ommand 7rite $!x $!x 2!x 2!x #!x #lock 3uspend #ycles $!x $!x 304 4 7% #!3 2!3 #3 #+% #,+ #+ t 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 "urst,ength#!3,atency 4 4 4 4 4 4
data sheet 41 rev. 1.4, 2006-01 10082003-l1gd-pvi5 hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram timing diagrams figure 25 power down mode and clock suspend "3 #lock3uspend #lock3uspend -ode%ntry -ode%xit !ddr $1- $1 !0 3tandby !ctive !ctivate "ank! #ommand (i : 2ead #ommand "ank! 2!x 2!x #!x 0ower$own 0ower$own -ode%xit -ode%ntry 304 %nd #lock-ask #lock-ask 3tart !x !x !x 0recharge #ommand "ank! !x t (: 0recharge 3tandby !ny #ommand 4 #!3 7% 2!3 #3 #+% #,+ #+ t 4 4 4 #+3 t 4 4 4 4 4 4 4 4 4 4 4 4 4 "urst,ength#!3,atency #+3 t 4 4 4 4 4 4
hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram timing diagrams data sheet 42 rev. 1.4, 2006-01 10082003-l1gd-pvi5 figure 26 self refresh (entry and exit) "3 t 3elf2efresh%xit #ommandissued !ddr $1- $1 !0 %ntry 3elf2efresh mustbeidle !ll"anks (i : ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 304 %xit#ommand "egin3elf2efresh 32%8 t 2# 3elf2efresh #ommand %xit !ny 4 #3 #!3 7% 2!3 #+% #,+ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ t #+3 4 4 4 ^ ^ ^ ^ 4 4 ^ ^ ^ ^ 4 4 4 #+3 t 4 4 4 4 4 4 4 4 4 4 4 4 4 4
data sheet 43 rev. 1.4, 2006-01 10082003-l1gd-pvi5 hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram timing diagrams figure 27 auto refresh (cbr) -inimum)nterval !ddr $1- $1 !0 "3 !uto2efresh #ommand !ll"anks 0recharge #ommand (i : t 20 t 2# 304 #ommand #ommand !uto2efresh #ommand "ank! !ctivate 2# t 2!x 2!x !x "ank! 2ead !x !x !x #!x 4 7% #!3 2!3 #3 #+% #,+ #+ t 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 "urst,ength#!3,atency 4 4 4 4 4 4
hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram timing diagrams data sheet 44 rev. 1.4, 2006-01 10082003-l1gd-pvi5 figure 28 cas latency = 2 !y !ddr "3 $1 $1- !0 !ctivate #ommand : (i "ank! 2!w 2!w #ommand 2ead #ommand "ank! 2ead "ank! !w !w #!w #!x 2ead "ank! #ommand !w !w !x !x !y #!y #3 7% #!3 2!3 #+% #,+ 4 #+ t 4 4 4 4 4 4 4 4 4 4 4 4 4 0recharge #ommand "ank! !y !y !ctivate #ommand "ank! 2!z 2!z 304 2ead "ank! #ommand #!z "urst,ength#!3,atency 4 4 4 4 4 4 4 4 4 !z !z !z !z
data sheet 45 rev. 1.4, 2006-01 10082003-l1gd-pvi5 hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram timing diagrams figure 29 cas latency = 3 !y #!w !ddr "3 $1 $1- !0 : (i "ank! !ctivate #ommand 2ead #ommand "ank! 2!w 2!w "ank! #ommand !w !w 2ead "ank! #ommand !w !w #!x 2ead !x !x !y 0recharge #ommand "ank! !y !y #!y #3 7% #!3 2!3 #+% #,+ 4 #+ t 4 4 4 4 4 4 4 4 4 4 4 4 4 "ank! 2ead #ommand !ctivate #ommand "ank! 2!z 2!z #!z 304 "urst,ength#!3,atency 4 4 4 4 4 4 4 4 4
hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram timing diagrams data sheet 46 rev. 1.4, 2006-01 10082003-l1gd-pvi5 figure 30 cas latency = 2 $"y !ddr "3 $1 $1- !0 !ctivate #ommand : (i "ank! 2!w 2!w #ommand 7rite #ommand "ank" 7rite "ank" $"w $"w #!w #!x 7rite "ank" #ommand $"w $"w $"x $"x $"y #!y #3 7% #!3 2!3 #+% #,+ 4 #+ t 4 4 4 4 4 4 4 4 4 4 4 4 4 0recharge #ommand "ank" $"y $"y !ctivate #ommand "ank" 2!z 2!z 304 2ead "ank" #ommand #!z "urst,ength#!3,atency 4 4 4 4 4 4 4 4 4 $"z $"z $"z $"z
data sheet 47 rev. 1.4, 2006-01 10082003-l1gd-pvi5 hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram timing diagrams figure 31 cas latency = 3 #ommand 7rite "ank" #"z $"w !ddr "3 $1 $1- !0 "ank" !ctivate #ommand : (i 2"z 2"z #ommand "ank" $"w $"w $"w 7rite "ank" #ommand $"x $"x #"x 7rite $"y $"y $"y 0recharge #ommand "ank" $"y #"y #3 7% #!3 2!3 #+% #,+ 4 #+ t 4 4 4 4 4 4 4 4 4 4 4 4 4 #ommand "ank" $"z !ctivate #ommand "ank" 7rite $"z 2"z 2"z #"z 304 "urst,ength#!3,atency 4 4 4 4 4 4 4 4 4
hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram timing diagrams data sheet 48 rev. 1.4, 2006-01 10082003-l1gd-pvi5 figure 32 cas latency = 2 !x t "3 !ddr $1 $1- !0 "ank" !ctivate #ommand (i : #ommand 2ead "ank" 2"x 2"x 2#$ t #"x 2ead !ctivate "ank! #ommand #ommand "ank" #ommand "x "x !# "x "ank! !ctivate "x "x 2!x 2!x #ommand 0recharge "ank" "x "x "x !x !x #!x 20 t 2"y 2"y #3 7% #!3 2!3 #+% #,+ 4 (igh t #+ 4 4 4 4 4 4 4 4 4 4 4 4 4 304 "ank" #ommand !x !x !x 2ead !x !x #"y "y "y "urst,ength#!3,atency 4 4 4 4 4 4 4 4 4
data sheet 49 rev. 1.4, 2006-01 10082003-l1gd-pvi5 hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram timing diagrams figure 33 cas latency = 3 !ctivate #ommand "ank! !ddr $1- $1 !0 "3 2ead "ank" #ommand #ommand "ank" !ctivate (i : "x "x #"x 2"x 2#$ t 2"x t !# !ctivate #ommand "ank" "x "ank! #ommand 2ead "x "x "x "x "ank" 0recharge #ommand !x "x !x !x 2!x #!x 2!x 20 t 2"y 2"y 0recharge "ank! #ommand !x 2ead "ank" #ommand !x !x !x !x 304 "y #"y 4 7% #!3 2!3 #3 #+% #,+ (igh #+ t 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 "urst,ength#!3,atency 4 4 4 4 4 4
hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram timing diagrams data sheet 50 rev. 1.4, 2006-01 10082003-l1gd-pvi5 figure 34 cas latency = 2 $"x $!x "3 !0 !ddr $1 $1- !ctivate #ommand "ank! (i : 7rite #ommand "ank! $!x 2!x 2!x 2#$ t #!x #ommand #ommand "ank" "ank! #ommand $!x $!x $!x "ank" !ctivate $!x $!x 2"x 2"x #ommand 0recharge "ank! 7rite $"x $!x $"x !ctivate $"x $"x 72 #"x t 20 t 2!y 2!y #,+ #+% #3 2!3 #!3 7% 4 (igh #+ t 4 4 4 4 4 4 4 4 4 4 4 4 4 #ommand "ank! 304 #ommand 0recharge "ank" $"x $"x $"x 7rite $!y $!y #!y 72 t $!y $!y $!y 4 "urst,ength#!3,atency 4 4 4 4 4 4 4 4
data sheet 51 rev. 1.4, 2006-01 10082003-l1gd-pvi5 hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram timing diagrams figure 35 cas latency = 3 $!x !ddr $1- $1 !0 "3 #ommand "ank! "ank! !ctivate #ommand (i : 7rite $!x $!x $!x $!x 2!x 2#$ t 2!x #!x $"x $"x 7rite #ommand "ank" "ank" !ctivate #ommand $!x $!x $!x 0recharge #ommand "ank! $"x $"x $"x #"x 2"x 2"x 72 t 20 t #ommand "ank! !ctivate #ommand "ank! 7rite $"x $"x $!y $"x 0recharge "ank" #ommand 304 $!y $!y $!y 72 2!y t #!y 2!y #!3 2!3 #+% #,+ 7% #3 4 (igh #+ t 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 "urst,ength#!3,atency 4 4 4 4 4 4 4
hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram timing diagrams data sheet 52 rev. 1.4, 2006-01 10082003-l1gd-pvi5 figure 36 cas latency = 2 #ommand !ctivate "ank! 4 "3 7rite$ataismasked ofa7rite"urst 0recharge4ermination !ddr $1 $1- !0 #ommand "ank! !ctivate (i : "ank! 7rite #ommand $!x $!x 2!x 2!x #!x #ommand "ank! #ommand 0recharge "ank! $!x $!x !ctivate 2!y 20 t 2!y !y #ommand "ank! 2ead "ank! 0recharge #ommand !y !y #!y 20 t 4 #3 7% #!3 2!3 #+% #,+ 4 (igh #+ t 4 4 4 4 4 4 4 4 4 4 4 4 0recharge4ermination ofa2ead"urst 304 "ank! #ommand 0recharge #ommand "ank! 2ead !z !z 2!z #!z 2!z !z 20 t "urst,engthor&ull0age#!3,atency 4 4 4 4 4 4 4 4
data sheet 53 rev. 1.4, 2006-01 10082003-l1gd-pvi5 hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram timing diagrams figure 37 full page burst read, cas latency = 2 "3 pageaddressbacktozero fromthehighestorder 4heburstcounterwraps duringthistimeinterval !ddr $1- $1 !0 ^ ^ (i : #ommand #ommand "ank! 2ead "ank! !ctivate "ank" "ank" #ommand #ommand !x !ctivate !ctivate !x !x ^ ^ !x 2!x 2!x #!x ^ ^ ^ ^ 2"x 2"x ^ ^ ^ ^ ^ ^ ^ ^ 304 burstingbeginningwiththestartingaddress "urst3top #ommand theburstcounterincrementsandcontinues terminatewhentheburstlengthissatisfied &ull0ageburstoperationdoesnot "ank" #ommand !x 2ead !x !x "x "x "x "x "x #"x "ank" #ommand !ctivate #ommand "ank" 0recharge "x "x 2"y t 20 2"y #!3 2!3 #+% #,+ #3 7% ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ (igh #+ t 4 4 4 ^ ^ ^ ^ 4 4 ^ ^ ^ ^ 4 4 4 4 4 4 4 4 4 4 4 "urst,ength&ull0age#!3,atency 4 4 4 4 4 4 4
hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram timing diagrams data sheet 54 rev. 1.4, 2006-01 10082003-l1gd-pvi5 figure 38 full page burst write, cas latency = 3 4 "x &ull0ageburstoperationdoesnot terminatewhentheburstlengthissatisfied burstingbeginningwiththestartingaddress theburstcounterincrementsandcontinues "3 #ommand "ank! !0 $1- $1 !ddr #ommand !ctivate "ank! (i : 2ead 2!x 2!x #!x pageaddressbacktozero duringthistimeinterval 4heburstcounterwraps fromthehighestorder !ctivate !ctivate "ank" "ank" #ommand #ommand !x !x !x !x ^ ^ ^ ^ 2"x 2"x ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ !x 2ead "ank" #ommand !x !x "x "x #"x 4 #,+ #+% #3 2!3 7% #!3 4 (igh #+ t 4 4 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 4 4 ^ ^ ^ ^ ^ ^ 4 4 4 ^ ^ 4 4 4 4 4 304 "ank" #ommand !ctivate "ank" 0recharge #ommand "urst3top #ommand "x "x "x 2"y t 22$ 2"y 4 "urst,ength&ull0age#!3,atency 4 4 4 4 4 4 4
data sheet 55 rev. 1.4, 2006-01 10082003-l1gd-pvi5 hyb39s512[40/80/16]0at(l) 512-mbit synchronous dram package outlines 6 package outlines figure 39 package outline p-tsopii-54-1 (top view) ? ? ? ? $ o e s n o t i n c l u d e p l a s t i c o r m e t a l p r o t r u s i o n o f m a x p e r s i d e x ? ? ? - ! 8 - ! 8 $ o e s n o t i n c l u d e p l a s t i c p r o t ru s i o n o f m a x p e r s i d e $ o e s n o t i n c l u d e d a m b a r p r o t r u s i o n o f m a x p e r s i d e ) n d e x - a r k i n g x - x ? ? ? ? ?
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